FIG. 10 is a cross sectional view of a conventional nitride read only memory (NROM) cell 100, which is a type of non-volatile memory (NVM) device that implements a silicon-oxide-nitride-oxide-silicon (SONOS) structure. NROM cell 100 includes p-type substrate 101, N+ source/drain (and diffusion bit line) regions 111 and 112, channel region 113, oxide-nitride-oxide (ONO) structure 120, bit line oxide regions 131 and 132, and an N-type polycrystalline silicon (“polysilicon”) control gate 140. ONO structure 120 includes lower (bottom) silicon oxide layer 121, silicon nitride layer 122 and upper silicon oxide layer 123. NROM cell 100 features two-bit per cell storage, with two data bits being stored in two separate charge trapping regions 122L and 122R in nitride layer 122. Thus, data is stored as charges in the ONO structure 120 at the edges of a memory transistor channel 113. NROM cell 100 is described in more detail in U.S. Pat. No. 5,768,192 to Eitan.
Programming NROM cell 100 requires increasing the threshold voltage of the cell. Programming typically involves applying a positive voltage to the gate 140 and a positive voltage to the drain (111 or 112) while the source (112 or 111) is grounded. The channel electrons are accelerated in the lateral field. The electrons eventually achieve sufficient energy to be injected into the silicon nitride layer 122, this being known as hot electron injection. When the drain and the gate voltages are no longer present, the bottom oxide layer 121 and the top oxide layer 123 of the ONO structure 120 prevent electrons from moving to the substrate 101 or the gate 140. An erase operation is performed by injecting holes generated in the drain (111 or 112) into the ONO structure 120 by a band-to-band tunneling mechanism. During erase operations, a positive voltage is applied to the drain (111 or 112) and a negative (or zero) voltage is applied to the gate 140. During read-out operations, the drain current is sensed in the direction “reverse” to the programming current, as indicated at the bottom of FIG. 10.
The major advantage of NROM cell 100 is the local charge trapping in charge trapping regions 122L and 122R, instead of in an entire floating gate structure as in conventional floating gate poly EEPROM cells. This local charge trapping arrangement enables NROM cell 100 to utilize significantly lower charge quantity to influence the cell threshold voltage Vt during read-out operations, in comparison to floating gate poly EEPROM cells. In addition, the local charge trapping arrangement facilitates “two bit operation”—i.e., programming the cell in different directions to store two bits of information in the single cell.
Although conventional NMOS cells provide many advantages over floating gate poly EEPROM cells, they also present unique problems. One problem associated with SONOS NMOS memory cells is that the charge trapping is not perfectly local; that is, some electrons are trapped far from drain edge (see FIG. 11), and these electrons cannot be erased efficiently using the conventional BBT erase process that generates local hole injection only near the drain. Thus, the endurance of NROM cells is limited due to the inability of the standard erase process to erase the parasitic electrons trapped in Bottom Oxide (BOX) and Nitride layers far from the drain edge. In addition, cell endurance is further limited by hot carrier degradation of the BOX layer due to hot carriers creating traps in the BOX layer during cycling, which are filled by the parasitic electrons, thus creating a closed positive feedback degradation loop (i.e., trap creation—electron trapping—erase voltage increases—more holes injected—more trap generation in the BOX layer far from the drain).
It is of great commercial importance to the manufacturers of NROM technology devices to provide NMOS cells that have a program/erase endurance of more than ten million cycles. Such endurance opens new business/marketing perspectives (for example, applications connected with recurrent storage of information, typical for automotive and image processing systems). Thus, there is a need for the manufacturers of NROM technology devices to overcome the parasitic electron trapping problem described above, thereby increasing the program/erase endurance of NROM devices to more than ten million cycles.
Conventional methods that attempt to address the problem of parasitic electrons trapped far from the drain edge are disclosed in U.S. Pat. No. 6,760,270 “Erase of a non-volatile memory” (herein “the Chindalore patent”), “A New Combination-Erase Technique for Erasing Nitride Based (SONOS) Nonvolatile Memories”, Chindalore et al., IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 4, APRIL 2003 Silicon Devices (herein “the Chindalore article”), U.S. Patent Pub. No. 20050237801 “Operation scheme with charge balancing for charge trapping non-volatile memory” (herein “the Shih patent”), and “A Novel 2-bit/cell Nitride Storage Flash Memory with Greater than 1M P/E-cycle Endurance”, Yen-Hao Shih, et.al., IEDM 2004 pg. 881 (herein “the Shih article”). These references generally teach hole injection from the substrate in NROM type device operation.
The approach taught in the Chindalore patent and article includes performing a hole injection procedure before the BBT erase process with the aim of decreasing the damage by BBT holes. This hole injection procedure involves thinning the BOX to 30 angstroms (30 A), and using a Fowler-Nordheim (F-N) erase stage at the beginning of each program/erase cycles. This approach has serious limitations. First, the F-N erase stage helps to discharge main distribution of electrons trapped in the drain region, but does not remove electrons trapped far from the drain. Second, the F-N erase stage strongly increases the erase time of NROM devices. Third, the voltages needed for erase are higher than in conventional NROM processes. Thus, this approach fails to overcome the parasitic electron problem in a manner that yields adequate program/erase endurance.
The approach taught in the Shih patent and article includes increasing the initial threshold voltage (Vt) of the memory cells above 3.5V by uniform F-N injection of electrons from the substrate using a positive gate voltage exceeding 20V. This approach makes a strong initial misbalance of electric fields in the ONO structure. The BOX layer field is initially high, which further allows enhancement by negative voltage at the polysilicon gate, and thus hole injection into the ONO structure. However, this approach also has serious limitations. First, increasing of the initial threshold voltage level assumes occupying of a large number of SiN traps. Thus, further large cycling windows can not be achieved due to the lack of available traps. Second, the readout voltage has to be strongly increased (above 4.5V to 5V), and thus additional high voltage circuitry is needed in design to support this voltage. Third, no protection circuits against plasma charging can be employed (otherwise the initial F-N p-injection is not feasible). Absence of protection makes the technology strongly dependent on Plasma potentials in the back/end of the process flow. The result is strong fluctuations of the initial threshold voltage, thus resulting in serious problems in array operation.
What is needed is an operating method and structure that increases the program/erase cycle endurance of NROM cells while avoiding the problems associated with the conventional approaches described above.